ESESC: A Fast Multicore Simulator

MIT Course 6.004 - Computation Structures

My solutions of Computer Systems: A Programmer’s Perspective, Third Edition (CS:APP3e) book, the text book for the course, CMU15-213: Introduction to Computer Systems.

A Fast DNN Accelerator Design Space Exploration Framework.

A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for architecture research and education.

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

HHRT: Hybrid Hierarchical Runtime library

Hardware compression for memory

A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies

A superscalar out-of‐order architectural simulator (With Memory Hierarchy).

Implementation of Hierarchy Oblivious Algorithms

AOS Agent is an open-source, multi-agent AI system that acts as your extended cognitive partner, featuring structured memory, specialized agents, and deep integration with various softwares via MCP.

A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

A loop test performance simulator for cache memories

The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

(ECE) A collection of helper scripts for the assignments for the course "Advanced Computer Architecture" [3.4.37.8]

A simulator of cache system behavior.

CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .

KV Memory Orchestrator — a browser-native research simulator for deterministic KV-cache residency, SRAM/HBM tiering, DMA scheduling, and memory-fabric orchestration in future transformer inference systems. Patent No. 202641062302, filed in India.