[hardware] 🐛 Zero-extend the vslideup.vi/vslidedown.vi immediate

[emiliengnr]

Hello, here is a pull request for a bug I found.

The Ara dispatcher sign-extends the 5-bit immediate of vslideup.vi and
vslidedown.vi (ara_req.stride = {{ELEN{rs1[19]}}, rs1}). The RISC-V vector spec
makes this immediate unsigned (16.3.1 and 16.3.2). For an immediate of 16 or
more the sign bit is set, so a small positive slide offset becomes a large
negative one, the slide moves the whole vector out of range and returns all
zeros, and the result diverges from Spike.

Changelog

Fixed

The fix zero-extends the immediate for the two slide cases (ara_req.stride =
{{ELEN{1'b0}}, rs1}). The signed scalar_op used by the other OPIVI instructions
is left unchanged, since their immediate is signed.

Checklist

• Automated tests pass
• Changelog updated
• Code style guideline is observed