Add stage-2 MMIO handler support#41
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m4tx
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This is a bit bigger than I originally anticipated. I'm wondering if we actually need to implement the entire instruction decoding functionality - I originally planned that maybe we could just get away with a generic data abort handler and leave the implementation of any specific behavior to the users of the project. On the other hand, perhaps most of them would end up implementing the same stuff anyway - unless there's some way to achieve data reads/writes for the guest easier somehow.
Because this touches way more aarch64 aspects than I'm comfortable reviewing, let's also see what @qwandor thinks.
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Pushed an update addressing the comments:
On the broader scope question: the current emulation remains syndrome-only, not a full trapped-instruction decoder. If the CPU does not provide a valid GPR-transfer syndrome ( Locally re-ran |
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Allow targets such as target/ritm.qemu_bl33.bin to build RITM with --cfg platform="qemu_bl33" directly from the target stem. This lets tests request a platform-specific binary without relying on the global PLATFORM setting.
Add the syndrome and IPA decoding as a standalone step before the stage-2 memory access handler support, so the following commit can focus on handler registration and dispatch.
The aarch64-rt exception frame only saved volatile registers, so a trapped memory access using x19-x28 as Rt could not be read or updated by the MMIO emulation path. That made otherwise valid guest load/store instructions fall through as unhandled Data Aborts. Provide a RITM-owned EL2 vector table and trap frame that saves x0-x30 before calling the Rust handler, while keeping HVC/SMC forwarding limited to the SMCCC x1-x17 argument ABI. Add integration coverage for filtered MMIO through x19 and x28.
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Summary
Tests
cargo fmt --all -- --checkgit diff --checkmake build PLATFORM=qemumake clippy PLATFORM=qemumake test PLATFORM=qemugit show --check upstream/main..HEAD