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Add stage-2 MMIO handler support#41

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zhangxp1998 wants to merge 4 commits into
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zhangxp1998:feature/stage2-mmio-handlers
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Add stage-2 MMIO handler support#41
zhangxp1998 wants to merge 4 commits into
google:mainfrom
zhangxp1998:feature/stage2-mmio-handlers

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@zhangxp1998

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Summary

  • Add stage-2 memory access handler support for trapping selected IPA ranges.
  • Add typed read/write handler APIs so write handlers cannot return read results.
  • Add a QEMU filtered MMIO test page and integration coverage.
  • Support platform-specific binary make targets.

Tests

  • cargo fmt --all -- --check
  • git diff --check
  • make build PLATFORM=qemu
  • make clippy PLATFORM=qemu
  • make test PLATFORM=qemu
  • git show --check upstream/main..HEAD

@zhangxp1998 zhangxp1998 requested a review from m4tx June 11, 2026 01:39
@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch 2 times, most recently from d17e460 to 47fa4e3 Compare June 11, 2026 02:24
@m4tx m4tx requested a review from qwandor June 11, 2026 11:41

@m4tx m4tx left a comment

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This is a bit bigger than I originally anticipated. I'm wondering if we actually need to implement the entire instruction decoding functionality - I originally planned that maybe we could just get away with a generic data abort handler and leave the implementation of any specific behavior to the users of the project. On the other hand, perhaps most of them would end up implementing the same stuff anyway - unless there's some way to achieve data reads/writes for the guest easier somehow.

Because this touches way more aarch64 aspects than I'm comfortable reviewing, let's also see what @qwandor thinks.

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Comment thread src/platform/qemu.rs Outdated
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Comment thread src/hypervisor.rs Outdated
Comment thread src/exceptions.rs Outdated
Comment thread src/hypervisor.rs Outdated
Comment thread src/hypervisor.rs Outdated
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@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch 2 times, most recently from 9e20948 to cd9e099 Compare June 11, 2026 14:32
@zhangxp1998

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Pushed an update addressing the comments:

  • align_up_to_page now uses next_multiple_of, and the helper names are now to_pages / to_ipa.
  • Moved the syndrome decode entry point to DecodedMemoryAccess::from_register_state.
  • Removed the per-data-abort Stage2Config lock by keeping only the IdMap behind a mutex; handler lookup is read-only after initialization.
  • When injecting an unhandled data abort back to EL1, ESR_EL1 now rewrites EC 0x24 (lower EL) to 0x25 (same EL).

On the broader scope question: the current emulation remains syndrome-only, not a full trapped-instruction decoder. If the CPU does not provide a valid GPR-transfer syndrome (ISV), we fall through to the normal guest Data Abort injection path. I left full writeback/SIMD support as part of the larger design question for @qwandor rather than expanding this PR further.

Locally re-ran cargo fmt --all -- --check, git diff --check, make build PLATFORM=qemu, make clippy PLATFORM=qemu, and make test PLATFORM=qemu.

@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch 3 times, most recently from 69f7b92 to d085967 Compare June 11, 2026 16:39
@zhangxp1998 zhangxp1998 requested a review from m4tx June 15, 2026 17:19

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Looks reasonable to me except two last nitpicks.

I can't find any obvious flaws, but as mentioned earlier, I'm not comfortable reviewing aarch64 internals used in this PR. Let's see what @qwandor says before merging this.

Comment thread src/hypervisor.rs Outdated
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@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch from d085967 to ba58a2c Compare June 16, 2026 16:07
Comment thread src/platform/qemu.rs Outdated
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Comment thread Makefile
Comment thread tests/memory_access_test/Cargo.toml Outdated
Comment thread tests/memory_access_test/src/lib.rs Outdated
Comment thread src/stage2.rs Outdated
Comment thread src/stage2.rs Outdated
Comment thread src/stage2.rs
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Comment thread src/stage2.rs Outdated
@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch 3 times, most recently from 2f04a0f to e1c7070 Compare June 18, 2026 20:00
Allow targets such as target/ritm.qemu_bl33.bin to build RITM with --cfg platform="qemu_bl33" directly from the target stem. This lets tests request a platform-specific binary without relying on the global PLATFORM setting.
Add the syndrome and IPA decoding as a standalone step before the stage-2 memory access handler support, so the following commit can focus on handler registration and dispatch.
The aarch64-rt exception frame only saved volatile registers, so a trapped memory access using x19-x28 as Rt could not be read or updated by the MMIO emulation path. That made otherwise valid guest load/store instructions fall through as unhandled Data Aborts.

Provide a RITM-owned EL2 vector table and trap frame that saves x0-x30 before calling the Rust handler, while keeping HVC/SMC forwarding limited to the SMCCC x1-x17 argument ABI. Add integration coverage for filtered MMIO through x19 and x28.
@zhangxp1998 zhangxp1998 force-pushed the feature/stage2-mmio-handlers branch from e1c7070 to e9afcbd Compare June 18, 2026 20:45
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3 participants