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Runtime Attestation

This project presents a generic, hardware-assisted runtime attestation system that can be adapted to various attestation configurations. The implemented hardware solution captures control-flow relationships and extracts feature representations during execution, significantly reducing system overhead and resource usage. The resulting design is well-suited for real-time monitoring in resource-constrained embedded environments.

This work was part of my Bachelor’s thesis.

Project Structure

  • top.sv
    Top-level module that integrates all submodules, including clocking, mapping, and neighbor tracking.

  • tb_top.sv
    Testbench for simulating and verifying the top-level design.

  • Hash.sv
    Implements a simplified version of the lookup3 hash function for 32-bit trace values, producing a 13-bit hash output.

  • MemoryController.sv
    Manages trace storage and lookup using a hash table implemented in BRAM.

  • NeighborTracker.sv
    Tracks and encodes neighbor relationships between traces, using URAM for storage.

Key Features

  • Trace Hashing:
    Efficiently hashes 32-bit trace values into 13-bit indices for fast memory operations.

  • Memory Management:
    Uses BRAM and URAM to store trace and neighbor data, with register buffers for recent entries.

  • Neighbor Tracking:
    Maintains and updates neighbor relationships for traces in real time.

Usage

  1. Simulation:
    Use the provided tb_top.sv testbench to simulate the design. Update file paths in the testbench as needed for your environment.

  2. Synthesis:
    Integrate the top-level module (top.sv) into your FPGA or ASIC project. Ensure all required IPs (e.g., clk_wiz_0, design_1_wrapper, hash_table) are included.

  3. Trace Input:
    Prepare trace input files (trace_values.txt, trace_values_no_duplicates.txt) as expected by the testbench.

File Descriptions


For more details, see the source code and comments within each module.

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